Introduction

Our goal at Applied Thin-Film Products (ATP), an ISO9001:2008 and AS9100C certified company, is to constantly evolve our processing and material capabilities to reflect our customers’ changing needs. Our state-of-the-art thin-film facility was founded in 1995 in the heart of Silicon Valley specifically for this purpose. ATP’s experienced personnel and representatives possess motivation and integrity, which is reflected by the reputation we enjoy in the military, aerospace, wireless, fiber-optic and medical life science marketplace.

In order to accommodate a growing global market, ATP expanded our manufacturing capacity in 2010 with the addition of a second facility located at 3620 Yale Way, Fremont, CA. This location is adjacent to the original existing building. Our Shanghai, China facility, which is now ISO9001:2008 certified, greatly enhances our operations for commercial manufacturing and assembly operations in the Pacific Rim.

ATP offers build-to-print services for a wide range of materials and metallization schemes. ATP fabricates circuits on substrates using As-Fired Alumina, Polished Alumina, Superstrate TPS, Aluminum Nitride, Beryllium Oxide, Fused Silica/Quartz, Sapphire and Hi-K Dielectrics.

 
 

Metallizations range from standard films to Aluminum, Chrome, Copper, Nickel, Gold, Palladium, Platinum, Titanium and Titanium Tungsten.

 

Circuit features can include fine pitch conductors, integrated resistors, vias, wrap-arounds, double sided patterning, polyimide supported bridges, hollow plated vias and solid filled vias.

 

Company Technologies Capabilities Design Guidelines Products Other

Introduction

Polyimide Supported Bridges

Photomasks

Standard Dimensions and Tolerances

Inductor Coils

Home

Quality Assurance System

Solder Dams

Substrates

Material and Conversion Tables

Inductor Coils Eng. Kit

Contact Us

Directions

Laser Diode Submounts (Au/Sn)

Material Specs

Thermal Performance

Microstrip Transmission Lines

Terms of Use

Employment

Vias: Plated Through

Laser Machining/Drilling-Vias

Aging Equation

Transmission Lines Eng. Kits

Privacy Policy

Sales Rep’s

Vias: Au or Cu Solid Filled

Backside Burnishing Treatment

Safe Current Limits

Stand Off/Isolation Pads

Facebook

Contact Us

Edge Wraps

Metallizations

Design Resources

ATP Bond Qualification Coupons

 
 

Gold Bumping

Integrated TaN Resistors

 

Product Samples

 
 

Fractal Fasten

Laser Resistor Trimming

 

Packaging/Chip Trays

 
   

Serialization